For example, in Japanese Patent Application Laid-Open Publication No. 2001-257567 (Patent Document 1), a circuit configuration of a voltage controlled oscillator enabling generation of a clock signal having a small jitter even when a power source voltage fluctuates in a PLL circuit including a phase comparator, a frequency comparator, a voltage controlled oscillator and the like is disclosed. In concrete, to a circuit configuration in which a ring oscillator and capacitance mutually connected in parallel and a MOS transistor controlling an oscillation frequency by controlling a power source voltage (current) thereof are equipped, a second means of controlling the oscillation frequency according to a phase comparison result is provided. This second means is realized by capacitance whose connection/disconnection to the ring oscillator can be switched. When this capacitance is connected according the phase comparison result, the oscillation frequency is lowered with increase of a load, and when it is not connected, an opposite result is obtained.
Further, in Japanese Patent Application Laid-Open Publication No. 2005-252723 (Patent Document 2), a PLL circuit having a structure in which a comparison result of a frequency comparator is reflected to a VCO (Voltage Controlled Oscillator) through processings by an integration circuit, a comparator and a gain adjustment circuit is described. This frequency comparator performs comparison and judgment of high/low of frequencies by observing change of a phase of an inputted clock using three phase periods obtained from 3-phase clocks from the VCO as references. Such a result of the frequency comparator is reflected to the VCO through various processings as described above, and thereby even if erroneous detection occurs in the frequency comparator, influence thereof can be reduced.
Furthermore, in Japanese Patent Application Laid-Open Publication No. 60-111528 (Patent Document 3), an integrated circuit device in which delay time of a logic circuit is monitored using a ring oscillator formed on a same LSI, a power source voltage of the LSI is controlled so that an oscillation frequency of this ring oscillator has a predetermined value, and thereby the delay time of the logic circuit is stabilized is described. In these processings, the number of oscillation times of the ring oscillator is counted by a cycle of, for example, an external clock signal, a result of comparison of the counted value with a predetermined value is integrated, and a rate of an on-state of a transistor connected to a power supply route is controlled using the integrated value.
And, in Japanese Patent Application Laid-Open Publication No. 62-125709 (Patent Document 4), a semiconductor integrated circuit having an FET and comprising means to control fluctuation of a threshold voltage during operation of the FET is described. In concrete, for example, a dummy FET is provided in a chip, a feedback loop circuit keeping a threshold voltage of this dummy FET constant is configured and the threshold voltage of the dummy FET under the feedback control is supplied also to the regular FET.